Nächste Seite: quine20241229.vhdl Aufwärts: Übungen Vorherige Seite: quine20241229_3x.vhdl
;; (C) David Vajda
;; Sun Dec 29 2024
;; Quine Mc Clusky - DNF - VHDL - caneda
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
2 0 0 1 0 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
Gruppe 1:
2 0 0 1 0 1
8 1 0 0 0 1
Gruppe 2:
6 0 1 1 0 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
2:6 0 - 1 0
2:10 - 0 1 0
8:10 1 0 - 0
8:12 1 - 0 0
6:7 0 1 1 -
10:11 1 0 1 -
2:10 - 0 1 0
2:6 0 - 1 0
8:12 1 - 0 0
8:10 1 0 - 0
6:7 0 1 1 -
10:11 1 0 1 -
2 6 7 8 10 11 12
2:10 + +
2:6 + +
8:12 + +
8:10 + +
6:7 + +
10:11 + +
2 6 7 8 10 11 12
2:10 + +
2:6 + +
8:12 + + p
8:10 + +
6:7 + + p
10:11 + + p
2 6 7 8 10 11 12
2:10 + +
8:12 + + p
6:7 + + p
10:11 + + p
2:10 - 0 1 0
8:12 1 - 0 0
6:7 0 1 1 -
10:11 1 0 1 -
y <= (not x2 and x1 and not x0) or
(x3 and not x1 and not x0) or
(not x3 and x2 and x1) or
(x3 and not x2 and x1);
library ieee;
use ieee.std_logic_1164.all;
entity quine20241229 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20241229 is
begin
y <= (not x2 and x1 and not x0) or
(x3 and not x1 and not x0) or
(not x3 and x2 and x1) or
(x3 and not x2 and x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20241229testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20241229testbench is
component quine20241229
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20241229 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
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