./vhdl20250308/quine3network20250307.txt

(C) David Vajda
Fri Mar  7 11:24:15 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		0
 2	0	1	0		0
 3	0	1	1		0
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		0
 7	1	1	1		1


	x2	x1	x0		y
 0	0	0	0		1
 4	1	0	0		1
 5	1	0	1		1
 7	1	1	1		1


 	x2	x1	x0		y
Gruppe 0:
 0	0	0	0		1
Gruppe 1:
 4	1	0	0		1
Gruppe 2:
 5	1	0	1		1
Gruppe 3:
 7	1	1	1		1

0:4			-	0	0
4:5			1	0	-
5:7			1	-	1


			0	4	5	7
0:4			+	+
4:5				+	+
5:7					+	+


			0	4	5	7
0:4			+	+
5:7					+	+

0:4			-	0	0
5:7			1	-	1

	y	<=	(not x1 and not x0) or
			(x2 and x0);

library ieee;
use ieee.std_logic_1164.all;

entity quine3network20250307 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine3network20250307 is
begin
	y	<=	(not x1 and not x0) or
			(x2 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine3network20250307testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine3network20250307testbench is
	component quine3network20250307
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine3network20250307 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);