Nächste Seite: Re: Aufgaben und Übungen, Aufwärts: Graphen, Schaltwerke und Zahlen Vorherige Seite: Re: Aufgaben und Übungen,
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
8 1 0 0 0 1
11 1 0 1 1 1
12 1 1 0 0 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
5 0 1 0 1 1
12 1 1 0 0 1
Gruppe 3:
11 1 0 1 1 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
5 0 1 0 1 1
12 1 1 0 0 1
Gruppe 3:
11 1 0 1 1 1
1:3 0 0 - 1
2:5 0 - 0 1
2:3 0 0 1 -
4:5 0 1 0 -
4:12 - 1 0 0
8:12 1 - 0 0
3:11 - 0 1 1
4:12 - 1 0 0
3:11 - 0 1 1
2:5 0 - 0 1
8:12 1 - 0 0
1:3 0 0 - 1
2:3 0 0 1 -
4:5 0 1 0 -
Gruppe 1:
4:12 - 1 0 0
Gruppe 2:
3:11 - 0 1 1
Gruppe 1:
2:5 0 - 0 1
8:12 1 - 0 0
Gruppe 1:
1:3 0 0 - 1
Gruppe 1:
2:3 0 0 1 -
4:5 0 1 0 -
4:12 - 1 0 0
3:11 - 0 1 1
2:5 0 - 0 1
8:12 1 - 0 0
1:3 0 0 - 1
2:3 0 0 1 -
4:5 0 1 0 -
1 2 3 4 5 8 11 12
4:12 * *
3:11 * *
2:5 * *
8:12 * *
1:3 * *
2:3 * *
4:5 * *
1 2 3 4 5 8 11 12
4:12 * *
3:11 * *
2:5 * *
8:12 * *
1:3 * *
4:12 - 1 0 0
3:11 - 0 1 1
2:5 0 - 0 1
8:12 1 - 0 0
1:3 0 0 - 1
y <= (x2 and not x1 and not x0) or
(not x2 and x1 and x0) or
(not x3 and not x1 and x0) or
(x3 and not x1 and not x0) or
(not x3 and not x2 and x0);
y <= not (
(not x2 or x1 or x0) and
(x2 or not x1 or not x0) and
(x3 or x1 or not x0) and
(not x3 or x1 or x0) and
(x3 or x2 or not x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0052 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0052 is
begin
y <= (x2 and not x1 and not x0) or
(not x2 and x1 and x0) or
(not x3 and not x1 and x0) or
(x3 and not x1 and not x0) or
(not x3 and not x2 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0052testbench is
port (
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0052testbench is
component meinschaltnetz0052
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
sn: meinschaltnetz0052 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
Ein Fehler ist noch drin, den märze ich jetzt aus
0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 1 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 0 14 1 1 1 0 0 15 1 1 1 1 0
Jetzt stimmt es. Schuld war ein falscher Name in der Benennung der Zeilen und - mit Auswirkungen, deswegen auf die Primimpikantentafel.
0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 1 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 0 14 1 1 1 0 0 15 1 1 1 1 0
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0052 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0052 is
begin
y <= (x2 and not x1 and not x0) or
(not x2 and x1 and x0) or
(not x3 and not x1 and x0) or
(x3 and not x1 and not x0) or
(not x3 and not x2 and x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0052testbench is
port (
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0052testbench is
component meinschaltnetz0052
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
sn: meinschaltnetz0052 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
8 1 0 0 0 1
11 1 0 1 1 1
12 1 1 0 0 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
5 0 1 0 1 1
12 1 1 0 0 1
Gruppe 3:
11 1 0 1 1 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
5 0 1 0 1 1
12 1 1 0 0 1
Gruppe 3:
11 1 0 1 1 1
1:3 0 0 - 1
1:5 0 - 0 1
2:3 0 0 1 -
4:5 0 1 0 -
4:12 - 1 0 0
8:12 1 - 0 0
3:11 - 0 1 1
4:12 - 1 0 0
3:11 - 0 1 1
1:5 0 - 0 1
8:12 1 - 0 0
1:3 0 0 - 1
2:3 0 0 1 -
4:5 0 1 0 -
Gruppe 1:
4:12 - 1 0 0
Gruppe 2:
3:11 - 0 1 1
Gruppe 1:
1:5 0 - 0 1
8:12 1 - 0 0
Gruppe 1:
1:3 0 0 - 1
Gruppe 1:
2:3 0 0 1 -
4:5 0 1 0 -
4:12 - 1 0 0
3:11 - 0 1 1
1:5 0 - 0 1
8:12 1 - 0 0
1:3 0 0 - 1
2:3 0 0 1 -
4:5 0 1 0 -
1 2 3 4 5 8 11 12
4:12 * *
3:11 * *
1:5 * *
8:12 * *
1:3 * *
2:3 * *
4:5 * *
1 2 3 4 5 8 11 12
4:12 * *
3:11 * *
1:5 * *
8:12 * *
2:3 * *
4:12 - 1 0 0
3:11 - 0 1 1
1:5 0 - 0 1
8:12 1 - 0 0
2:3 0 0 1 -
y <= (x2 and not x1 and not x0) or
(not x2 and x1 and x0) or
(not x3 and not x1 and x0) or
(x3 and not x1 and not x0) or
(not x3 and not x2 and x1);
y <= not (
(not x2 or x1 or x0) and
(x2 or not x1 or not x0) and
(x3 or x1 or not x0) and
(not x3 or x1 or x0) and
(x3 or x2 or not x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0052 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0052 is
begin
y <= (x2 and not x1 and not x0) or
(not x2 and x1 and x0) or
(not x3 and not x1 and x0) or
(x3 and not x1 and not x0) or
(not x3 and not x2 and x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0052testbench is
port (
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0052testbench is
component meinschaltnetz0052
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
sn: meinschaltnetz0052 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;